The invention relates to an integrated memory circuit which includes a plurality of memory blocks with memory cells which are arranged in rows and columns, the memory cells which are arranged in a column being selectable via a column selection line, the memory cells of various memory blocks which are arranged in a row being selectable via a row selection line, a row of memory cells in a memory block being activatable via a logic row selection gate whereto a row selection signal and a block selection signal are applied.
A memory circuit of this kind is known from ISSCC, Digest of Technical Papers, February 1983, pp. 58-59. The subdivision of a memory into memory blocks with block selection (in the row direction and/or the column direction) is particularly advantageous for memories having a capacity of 128 kb and more (256 kb etc.). As a memory is made larger, the effect of the capacitance of the bit lines and the word lines will be greater. The charging and discharging of these lines will then be slower. This problem is avoided by subdividing a memory into blocks with selective activation per block. In the known circuit the block selection signal BS and the row selection signal RS are applied to an AND-gate for the selection of a row of memory cells in a memory block. In practice an AND-gate is realized by connecting an inverting amplifier to the output of an inverting AND-gate, so that the circuit becomes large (6 transistors) and slow (due to two gate delays). Another possibility would consist of the selection of a row in a memory block by means of an inverting OR-gate which then receives the inverted block selection signal BS and the inverted row selection signal RS. In the case of CMOS transistors this solution again leads to a slower block selection circuit, because the PMOS transistors must be made wider in order to realize the same power supply as for the AND-gate, so that the input capacitances become higher. The inverting OR-gate switches quickly, but more time will be required for charging these input capacitances. For example, in a 256 kb memory, the block selection signal BS activates a number of 256 (or 512, 1024, depending on the organization of the memory) block selection circuits in parallel.